Creonic’s oFEC IP cores deliver high coding gain through a fully parallel, pipelined decoder architecture with 3 soft-decision (SD) and 2 hard-decision (HD) decoding steps. It supports data rates from 200G to 800G, including Probabilistic Constellation Shaping (PCS) modes to enhance spectral efficiency, noise tolerance, and transmission reach. In addition to the FEC engine, the solution includes an interleaver/deinterleaver and parallel CRC checks for final payload validation. An FPGA version operating at 10 Gbps is available for prototyping, testing, and lower-bandwidth use cases.