5G NR is the mobile broadband standard of the 5th generation. A new rate compatible structure for LDPC codes are employed for channel coding to fulfill the broad applications supported by the standard. Creonic’s 5G LDPC Decoder and Encoder IP cores provide a perfect solution for this new LDPC structure with high level of flexibility while maintaining high throughput and low latency as required by the standard.  

The Creonic SDA OCT Encoder handles the construction of Over-The-Air (OTA) frames as indicated in the standard, a preamble followed by a header and payload data, with both fields being protected by cyclic redundancy check (CRC) and forward error correction (FEC). The Creonic SDA OCT Decoder performs the synchronization of the Over-The-Air (OTA) frame and then decodes the header and payload data within the frame.  

The Creonic DVB-S2X Wideband Modulator is a low-complexity high-performance solution that allows for symbol rates of up to 500 MSymb/s (4 Gbit/s for 256-APSK) on state-of-the-art FPGAs. The IP core performs all tasks of the inner transmitter and complements the Creonic DVB-S2X Wideband Receiver Solutions (DVB-S2X Wideband Demodulator and DVB-S2X LDPC/BCH Wideband Decoder). The modulator expects BBFrames after mode adaptation as input and performs stream adaptation, FEC encoding, mapping, PL framing and modulation. In addition, the core can perform baseband interpolation and output gain adjustment. The output of the core is designed to be followed by a DAC and RF front end.

The Creonic DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver while processing up to 36 carriers in parallel. The demodulator expects quantized real samples in an intermediate frequency (IF) from an analog-digital-converter (ADC). It separates the carriers with FFT/IFFT processing, and then performs all further demodulation steps in a time-multiplexed way. It recovers timing, frequency and phase of the complex mapped symbols for each carrier individually. In addition, the core handles PL frame recovery and PL deframing. 

Creonic’s oFEC IP cores deliver high coding gain through a fully parallel, pipelined decoder architecture with 3 soft-decision (SD) and 2 hard-decision (HD) decoding steps. It supports data rates from 200G to 800G, including Probabilistic Constellation Shaping (PCS) modes to enhance spectral efficiency, noise tolerance, and transmission reach. In addition to the FEC engine, the solution includes an interleaver/deinterleaver and parallel CRC checks for final payload validation. An FPGA version operating at 10 Gbps is available for prototyping, testing, and lower-bandwidth use cases.